1. Field of the Invention
The present invention relates to an address designating method of a memory and an apparatus therefor. More specifically, the present invention relates to an address designating method of a memory for use in interleaving or deinterleaving the data using a memory on a block unit basis and an apparatus for performing the same.
2. Description of the Prior Art
Of late, an error correcting code has been employed to obtain a reproduced sound of a high quality in a PCM recorder, a PCM audio disc, and the like. Such an error correcting system using an error correcting code is performed by secting a word series of sampled signals obtained by sampling an analogue signal into a plurality of words or a plurality of blocks of frame, by implementing one error correcting block by adding an error correcting word to each block, and by making correction on the occasion of reproduction with respect to an erroneous word on a transmission line. However, there is a limit to such error correcting system and it becomes impossible to make correction when almost all words in one error correcting block are in error due to occurrence of a burst error on a transmission line.
Conventionally, as a countermeasure to a burst error, error correction was made by interleaving in which the respective words in the error correcting block are dispersed on the occasion of recording, by recording the respective words at given intervals on a recording medium, and by deinterleaving for restoring the same to the original arrangement on the occasion of reproduction.
FIG. 1 is a diagram showing a data format for explaining the processing for interleaving and deinterleaving which constitutes the background of the present invention. Referring to the figure, one error correcting block is shown, in which one frame is assumed to be one block and one block comprises eight words of D0 to D7. In such a case, group 1 shows the N-th error correcting block including eight words of D0 to D7, wherein an error correcting code is added to a sampled signal word, where N is an integer. For example, the words D0 to D5 constitute the data and the words D6 and D7 constitute an error correcting code. Group 2 shows a delay amount of the respective words D0, D1, D2 to D7 in one block and the same is determined as 0, d, 2d to 7d, where d denotes a unit delay amount of the integer and is selected to be a data transmission time of one word, for example. In the following description, d=16 is assumed by way of one example. In interleaving, the respective words D0 to D7 in one block are delayed by a delay amount corresponding to the respective words. Group 3 shows a word structure of one block after interleaving. After processing of interleaving, each block is constituted with the words which were in the error correcting block of a different number and the same is recorded on a recording medium such as a record disc. Group 4 shows a delay amount per each word in the case where the data as interleaved as described previously is to be deinterleaved. The delay amount on the occasion of the deinterleaving is selected to be a value which is reverse proportional to the delay amount on the occasion of interleaving. For example, in the case where the delay amount on the occasion of interleaving is selected to be 0, d to 7d for the words D0, D1 to D7, respectively, the delay amount on the occasion of deinterleaving is selected to be 7d, 6d to 0, respectively. Group 5 shows a format of one error correcting block after the processing of deinterleaving was performed. As is clear from the illustration, the respective words D0 to D7 all become equal to the words of the (N-7d)-th error correcting block and this means that a combination before interleaving was regained, except for the point of the delay amount 7d.
If and when the processing of interleaving and the processing of deinterleaving as shown in FIG. 1 are performed, even if a burst error occurs on a transmission line and an error of the length of eight words of the block shown by group 3 has occurred, erroneous words are dispersed by performing the processing of deinterleaving and therefore an error of only one word is merely caused in one block obtained by the processing of deinterleaving, whereby correction can be made. In order to achieve the processing of such interleaving and deinterleaving, an approach is employed in which the word data of one block is once stored in a memory and thereafter the respective words are read out in a predetermined sequence. In the following, an addressing control of the memory on the occasion of performing the interleaving and the deinterleaving will be described.
First, a description will be made of a case where the deinterleaving is performed. FIG. 2 is a block diagram of a conventional address designating apparatus of a memory in the case where the processing of deinterleaving is to be performed. Referring to the figure, an address designating apparatus 10 comprises a write address designating circuit 101 and a read address designating circuit 102. Now a specific structure of the address designating apparatus 10 will be described. A write sample clock WS (hereinafter referred to as a clock WS) is applied to an input terminal 11a. The clock WS is applied to an addition input terminal UP of a counter 12. The counter 12 has a three-bit output and makes an addition operation upon each receipt of the clock WS, whereby a count value thereof is withdrawn as write addressing data corresponding to the words in one block. A write block change clock WB (hereinafter referred to as a clock WB) is applied to an input terminal 11b. The clock WB is applied to a reset input terminal R of a counter 12 and is also applied to an addition input terminal UP of a counter 13. The write addressing of a memory 40 is determined by the output from these counters 12 and 13. More specifically, the output from the counter 12 is applied to a selector 14 as write address data for designating the three less significant bits of the memory 40. The output from the counter 13 is applied to the selector 14 as write address data designating the more significant address of the memory 40.
A read sample clock RS (hereinafter referred to as a clock RS) is applied to an input terminal 11c. The clock RS corresponds to eight words in one error correcting block. The clock RS is applied to both the addition input terminal UP of the counter 15 and the addition input terminal UP of the counter 16. The counter 15 has a three-bit output and makes an addition operation upon each application of the clock RS and is reset responsive to the clock RB applied to the input terminal 11d. The clock RB serves as a read block changing clock and is applied one by one as the number of the error correcting block proceeds. The clock RB is applied to the addition input terminal UP of the counter 17. The counter 17 has a four-bit output and provides a carry output from the carry output terminal CA to the addition input terminal UP of a counter 18. The counter 18 provides the count value to the parallel load input of the counter 16. The counter 16 is supplied with the load clock LD being applied to the input terminal 11e. The read address of the memory 40 is determined as a function of the outputs from these counters 15 to 17. More specifically, the output of the counter 15 is obtained as read address data designating the address of the less significant three bits. The outputs from the counters 16 and 17 are obtained as read address data designating the more significant address of the memory. The read address data is applied to the selector 14.
The selector 14 serves to selectively provide the write addresses or the read addresses in response to the select signal SL applied to the input terminal 11f. The write address data or the read address data selected by the selector 14 is obtained from the output terminal 11g as the address data of the memory and is applied to the memory 40.
An initial setting circuit 19 is supplied with the outputs from the counters 17 and 18. The initial setting circuit 19 provides an output for setting the count value of the counter 13 to be 7d when the value determined by the output of the counters 17 and 18 is 0.
Before entering into a detailed description of the operation of the address designating apparatus shown in FIG. 2, an outline of the operation will be described with reference to FIG. 3, which is a diagrammatic view of a memory map per one bit in one word on the occasion of deinterleaving. A more significant address value has been selected as row addresses and an address value of the less significant three bits has been selected as column addresses. A triangle mark denotes the write data and a circle mark denotes the read data. The writing of the data is performed by maintaining the row addressing in a predetermined value and by changing one by one the column addressing from 0 to 7. The same is performed by renewing the row addressing one by one. The figure shows a case where the data (D0, N), (D1, N-d), (D2, N-2d), (D3, N-3d), (D4, N-4d), (D5, N-5d), (D6, N-6d) and (D7, N-7d) are written in succession in the row address 7d and the column addresses 0 to 7. The reading of the data is performed by changing one by one the column addressing from 0 to 7 each time d is added to the row addressing obtained by subtracting 7d from the row addressing on the occasion of the writing. The same is performed by renewing one by one the row addressing. The figure shows a case where the data (D0, N-7d), (D1, N-7d), (D2, N-7d), (D3, N-7d), (D4, N-7d), (D5, N-7d), (D6, N-7d) and (D7, N-7d) of the addresses (0, 1), (d, 1), (2d, 2), (3d, 3), (4d, 4), (5d, 5), (6d, 6) and (7d, 7) are in succession read out. The data as read out are those deinterleaved.
Now the operation of the address designating apparatus shown in FIG. 2 will be described in detail with reference to FIGS. 3 to 5. FIG. 4 is a time chart for explaining the operation of the write address designating circuit 101 and FIG. 5 is a time chart for explaining of the operation of the read address designating circuit 102.
First, the operation of the write address designating circuit 101 will be described mainly with reference to the FIG. 4 time chart. The example shown in the figure shows a case where the eight words in one transmission block (the group 3 shown in FIG. 1) are written by maintaining the more significant address to be constant and by changing the less significant address from 0 to 7 and the next block is written after the more significant address is advanced by one by the clock WB.
At the timing t1 the counter 12 is reset by the clock WB and at the same time one is added to the counter 13. Therefore, the output OUT12 from the counter 12 becomes 0 and at the same time the output OUT13 of the counter 13 is changed from the value assumed immediately before, say 7d-1 to the new value 7d.
At the timing t2 the count value of the counter 12 is advanced by one upon application of the clock WS, thereby to provide 1. At that time, the data of the leading word (D0, N) in the N-th block in the write data WDATA is written in the memory during a period between the timing t1 and the timing t2. The address thereof is (m, n), assuming the more significant address value is m and the less significant address value is n. In such case, the value of the output OUT13 of the counter 13 becomes the more significant address value m and the output 0 of the counter 12 becomes the less significant address value n and therefore the address is (7d, 0). The data of the next word (D1, N-d) is written in the address (7d, 1). Likewise thereafter, the address of the less significant three bits is incremented one by one for each word and the data of the word D2 to D7 is written in the write addresses determined by the output OUT13 of the counter 13 and the output OUT12 of the counter 12. When the writing of the data of the eight words is completed at the timing t3, the clock WB is applied. Therefore, the count value of the counter 13 is advanced by one and the more significant address m becomes 7d+1 and the data of the respective words in the next (N+1)-th block is in succession written. Meanwhile, in actuality the count value of the counter 13 in such a case reaches the upper limit and the count value returns to 0 and the more significant address m also returns to 0.
Now the operation of the read address designating circuit 102 will be described with reference to the FIG. 5 time chart.
When the clock RB is applied at the timing t1, the counter 15 is reset and the output OUT15 thereof becomes 0. As a result, the less significant read address becomes 0. On the other hand, the counter 13 has a value 7d initially set by the initial setting circuit 19 and the more significant address of the read address designating circuit 101 is set to be delayed by 7d as compared with that of the write address designating circuit 102. Therefore, if and when the more significant address of the write address designating circuit 101 is 7d, the more significant read count value MRCV constituted by the count value of the counter 17 and the count value of the counter 18 is 0. More specifically, the initial setting circuit 19 is for avoiding a conflict between the write addresses and the read addresses of the memory. Without the initial setting circuit 19, both the write addresses and the read addresses would have started from random addresses upon turning on a power supply, whereby a combination of the read data would not have become normal. If once the initial value 7d is set by the initial setting circuit 19, both the write and read addresses make circulation in the memory with a predetermined relation maintained, in the case where the write and read frame frequencies are the same.
When the load clock LD is applied to the input terminal 11e at the timing t4, 0 is loaded in the counter 16. Therefore, the more significant read address m becomes zero and as a result the read address becomes (0, 0). At that time the data (D0, N-7d) which is 7d block before the data (D0, N) is read from the memory 40, as shown in FIG. 3.
When the clock RS is applied at the timing t5, the output OUT15 of the counter 15 becomes 1. At the same time, the counter 16 is advanced by one. This means that the more significant read address m is advanced by d. Therefore, the read address of the memory becomes (d, 1) and the data (D1, N-d-6d)=(D1, N-7d) is read out from the memory 40.
Likewise thereafter, the count values of the counters 15 and 16 are advanced one by one by the clock RS and the data stored in the address designated by both count values is read out, whereby the word arrangement of the (N-7d)-th error correcting block shown by the group 5 in FIG. 1 can be eventually attained.
The interleaving is continuously performed by making the above described operation with the write system and the read system synchronized with each other and with the phase of the clock adjusted such that the data of the word D7 is read after the same is written. In the FIG. 1 example the data of the clock shown in the group 3 is written in the more significant address 7d and then the data of the next block is written in the address of the more significant address 0, whereupon the data (D7, N-7d) of the read address (7d, 7) is read and then the data (D0, N-7d+1) of the leading word of the next error correcting block starts to be read from the address (1, 0), whereby the deinterleaving can be done through circulation of the memory of 8.times.(7d+1) bits per one bit, where 8 corresponds to the less significant address number and 7d+1 corresponds to the more significant address number. (See FIG. 3.)
In the foregoing a description was made of the address control of the memory on the occasion of the deinterleaving. Although the address control of the memory on the occasion of the interleaving can be readily understood from the foregoing description, a brief description thereof will be made in the following for clarification.
FIG. 6 is a view diagrammatically showing a memory map per one bit in one word on the occasion of the interleaving. Now a difference from the FIG. 3 illustration will be mainly described. The writing of the data is performed by maintaining the row addressing in a predetermined value and by changing the column addressing one by one from 0 to 7. The same is also performed by renewing one by one the row addressing. These are the same as in the case of the deinterleaving. The figure shows a case where the data (D0, N), (D1, N), (D2, N), (D3, N), (D4, N), (D5, N), (D6, N) and (D7, N) are in succession written in the row address 7d and the column addresses 0 to 7. The reading of the data is carried out by changing one by one from 0 to 7 the column addressing each time d is subtracted from the row addressing on the occasion of the writing. The same is carried out by renewing one by one the row addressing. The figure shows a case where the data (D0, N), (D1, N-d), (D2, N-2d), (D3, N-3d), (D4, N-4d), (D5, N-5d), (D6, N-6d) and (D7, N-7d) is in succession read out from the addresses (7d, 0), (6d, 1), (5d, 2), (4d, 3), (3d, 4), (2d, 5), (d, 6) and (0, 7). The delay amount shown in group 2 of FIG. 1 is thus obtained and the interleaving is performed.
In order to achieve the above described interleaving using the address designating apparatus shown in FIG. 2, a down counter may be used in place of the counter 16. Accordingly, the details of the operation of the FIG. 2 address designating apparatus on the occasion of the interleaving will be understood by referring again to FIGS. 4 and 5 and the description in conjunction therewith by taking into consideration the above described alteration.
However, in the case where the interleaving or the deinterleaving as shown in FIG. 1 is to be performed, a minimum indispensable memory capacity per one bit in the word is 28d bits which are the total of the respective delay amounts 0 to 7d, whereas in the case where the FIG. 2 conventional address designating apparatus is to be employed, a memory capacity of 8.times.(7d+1) bits per one bit in the word was required as described previously, namely a memory capacity as large as two times the minimum indispensable memory capacity was required and uneconomical. Accordingly, it was desired that an addressing method and apparatus of a memory capable of performing the interleaving and the deinterleaving with a memory capacity which is close to the minimum indispensable memory capacity is provided.